The Storage and Memory Signal

Direction: Worsening.

This period: Samsung told industry contacts on September 20 that it plans to raise monthly HBM wafer input by roughly 40%, from about 180,000 to about 250,000, and lift HBM4/HBM4E's share of total HBM output from roughly 40% to roughly 80% next year, corroborated by a 2.5x jump in outsourced glass-carrier cleaning demand tied to that ramp. That's more conventional-DRAM-capable capacity converting to HBM, not less. Working against that read, TrendForce logged spot DRAM and NAND prices cooling at the margins the week of September 14-21, with DDR5 inquiries slowing and the 512Gb TLC NAND wafer spot price down 1.00% week over week to $19.883. That's soft consumer-segment spot trading, though, not the enterprise contract pricing and HBM allocation this call actually tracks.

Driver: HBM production is still eating disproportionately into wafer capacity that would otherwise make conventional DRAM and NAND, the same driver this newsletter has tracked since Issue 03, now visible directly in Samsung's own capacity-shift plan rather than only in an analyst's inventory estimate.

Watch for: Micron's fiscal Q4 2026 earnings call on September 30, its first public update on the reported 60K-wafer HBM capacity ramp toward 100K by year end and the first chance to address whether DeepSeek's KV-cache efficiency claims are showing up in bulk orders.

Reuters reported this week, citing people familiar with the matter, that Solidigm is meeting with investment banks in a competitive process for IPO roles, weighing a US listing that could come as early as 2027 at a valuation of up to $150 billion, raising as much as $15 billion in the offering. That would be among the largest semiconductor listings ever attempted in the US. Bloomberg's own reporting on the same broader story put Solidigm's valuation closer to $100 billion, a $50 billion gap that neither outlet has reconciled. SK hynix's official response hasn't moved: Solidigm "is reviewing various options to strengthen its business competitiveness," the company said, "but no specific plans have been confirmed," language nearly identical to what it said about the same review in August and again in September.

The gap between $100 billion and $150 billion is worth sitting with rather than averaging away. Both figures came from sourcing, not a filed prospectus, which means both are somebody's model of what the market will pay, built before a banker has run a single roadshow. A $50 billion spread on a single company's valuation is enormous by the standards of pre-IPO reporting, and it says more about how unsettled Solidigm's own numbers are internally than it does about investor appetite. NAND pricing has been on a historic run this year, per this newsletter's own Index, but a NAND-only business is also the most cyclical corner of the memory industry, and whichever number sticks will be set at the top of a pricing cycle that even Kioxia's own CEO has publicly said he wants to cool down.

Then there's the fab problem, which this newsletter flagged just last issue and which neither wire report addresses. Solidigm's only NAND fab sits in Dalian, China, restricted by US export controls to sub-200-layer NAND, a full generation behind what Samsung, SK hynix's own domestic lines, and Micron are shipping. As of last week, Solidigm hadn't picked a US site, hadn't gotten an approval, and hadn't set a construction timetable, despite scouting upstate New York as a leading candidate. A $150 billion IPO story and a fab search that's still in the site-visit stage are happening in the same company, in the same month, and only one of those two processes has a hard deadline that matters to customers: whoever actually builds current-generation NAND capacity on US soil first captures the supply security premium that export controls have created. An IPO raises capital. It doesn't pour concrete.

Read the whole thing as two bankers' stories layered on top of one operational reality. SK hynix gave itself until on or around November 5 to detail Solidigm's strategic review, a deadline this newsletter has now tracked across three issues without it slipping. That date, not this week's valuation chatter, is the one that will say whether any of this becomes a filed S-1 rather than sourced reporting with a moving number attached.

CXMT announced mass production of what it calls its G5 platform at the World Manufacturing Convention in Hefei on September 20, its fifth-generation DRAM technology. The headline spec is an 11.95-nanometer active-area half-pitch for the memory array, achieved with quadruple patterning rather than the extreme ultraviolet lithography Samsung, SK hynix, and Micron all use at equivalent nodes and that US export controls bar CXMT from buying. Quadruple patterning means exposing and etching a wafer four separate times to draw features fine enough that a single EUV exposure would otherwise handle in one pass, trading tool cost for process complexity and, typically, yield.

CXMT's own numbers claim at least 50% more dies per wafer than its fourth-generation platform, a real density gain by any measure, plus two 24Gb LPDDR5X products already shipping in volume for smartphones. That's a mobile-memory launch, not a server-DRAM or HBM one, which matters for how directly this touches the AI infrastructure story this newsletter otherwise tracks. CXMT is not announcing an HBM competitor this week. It's announcing that its DRAM roadmap can keep advancing node over node using tools it's actually allowed to buy, which is a different and in some ways more durable claim than a one-off product spec.

The context that makes this worth a Second Cut rather than a passing mention is the timing against Samsung's news in this same issue. Samsung is adding roughly 70,000 wafers a month of HBM capacity specifically because AI demand keeps pulling conventional DRAM-capable capacity toward HBM. CXMT is demonstrating that a company locked out of EUV can still add DRAM density through brute-force patterning, at the cost of process complexity nobody has disclosed a yield figure for. Whether that trade-off scales to the higher-density, higher-speed parts servers and HBM stacks actually need is the real open question, and it's one CXMT's own announcement doesn't answer. A phone-memory launch built on export-control workarounds is a proof of concept for China's DRAM independence, not evidence that the workaround closes the gap with Samsung, SK hynix, or Micron at the nodes that matter for AI infrastructure.