The Storage and Memory Signal

Direction: Worsening.

This period: Samsung and SK hynix's combined finished-goods memory inventory fell below 10 days of supply in the third quarter, the tightest level on record, according to a KB Securities note cited across Korean and Asian trade press on September 7. Analyst Kim Dong-won pointed to HBM4 production, which consumes roughly three times the wafer capacity per bit that standard DRAM does, as the mechanism draining the buffer. IDC's Q2 2026 enterprise storage systems tracker, published September 10, corroborated the squeeze from the buyer's side, attributing part of a 33.6% year-over-year revenue jump to rising NAND and DRAM component costs pulling forward hardware refresh spending rather than more capacity purchased for the same money.

Driver: HBM production is still eating disproportionately into wafer capacity that would otherwise make conventional DRAM and NAND, the same driver this newsletter has tracked since Issue 03, now quantified at roughly 3x the wafer input per bit for HBM4 specifically.

Watch for: Micron's fiscal Q4 2026 earnings call on September 30, its first public update on the reported 60K-wafer HBM capacity ramp and the first chance to address whether DeepSeek's KV-cache efficiency claims are showing up in bulk orders.

Bloomberg reported September 14 that Kioxia is considering raising at least $10 billion through a US listing of American depositary receipts, working with Bank of America, Goldman Sachs, and JPMorgan on an offering that could land as early as the April-to-June window of 2027. The Tokyo-based NAND maker already has an ADR registration on file with the SEC. Its stock has climbed roughly 900% since the start of 2026 on AI-driven SSD demand, recently crossing ¥100,000 a share, and a 3-for-1 split takes effect September 30. Kioxia's own reasoning, per Bloomberg's sourcing, is straightforward: more liquidity after repurchasing billions of dollars of its own shares in Japan, and a shot at joining a semiconductor-focused US index that Japanese exchanges can't offer.

Four days later, Reuters reported that Solidigm, SK hynix's NAND subsidiary, is reviewing candidate sites for a NAND mass-production line on the US East Coast, with upstate New York named as a leading contender. Nothing is close to final. No factory has been approved, no site has been chosen, and no construction timetable exists; SK hynix and Solidigm each responded to the report with language nearly identical to what SK hynix said about the Solidigm IPO review back in August, something to the effect of reviewing options to strengthen competitiveness, with nothing determined.

The reason both stories are landing now is the same constraint, even though the two moves look nothing alike on paper. Solidigm's only NAND fab sits in Dalian, and US export controls bar it from running the advanced equipment needed to produce anything newer than what Reuters describes as sub-200-layer, 100-layer-class NAND, the same generation as its existing Plant 1, even as a second Dalian plant comes online. That's not a paperwork problem. It means Solidigm is stuck building yesterday's NAND on Chinese soil no matter how much capacity it adds there, while Samsung, SK hynix's own domestic lines, and Micron keep advancing. A US-based fab would let Solidigm actually build current-generation NAND, and as a side benefit, insulate it from whatever the next round of tariffs or export restrictions brings.

Kioxia's motivation runs in a different direction but rhymes. It isn't short on manufacturing access; its constraint is capital markets. A stock that's run 900% wants a bigger, deeper pool to trade in than Tokyo alone offers, and an ADR listing is the standard way a foreign company taps that pool while also opening the door to inclusion in US semiconductor indexes that institutional money tracks passively. Put the two stories side by side and the pattern is capital and manufacturing access sitting in the wrong geography for the AI memory cycle happening right now, and two companies moving, cautiously, to fix that on American soil.

Caution belongs here too. Neither story is a done deal. Kioxia's plan came from Bloomberg sourcing people familiar with the matter, not a company announcement, and Bloomberg's own reporting flagged that size, bank lineup, and timing could all still change. Solidigm's fab search came from Reuters sourcing as well, and at least one trade outlet explicitly noted no site has actually been approved or selected, pushing back on breathless framing elsewhere. Read both as real signal of intent from two companies that have spent all year benefiting from a memory shortage and now have the balance sheets and the motive to act on it, not as done deals.

HPE's Alletra Storage MP X10000 Release 4 went generally available September 17. It doubles cluster size to 16 nodes and 16 JBOFs, roughly doubling both raw capacity, to about 23PB, and performance versus the prior release. It extends the platform's RDMA acceleration from object storage to file storage and adds native-namespace NFS alongside object with no translation layer in between, plus support for Nvidia's GPUDirect Storage. The number HPE is leading with, though, is a KV cache figure: independent testing cited by the company found up to 20x faster time-to-first-token and up to 17x higher effective inference throughput when the array handles KV cache offload over RDMA and GPUDirect rather than a generic storage path.

This isn't a novel idea anymore. It's a pattern this newsletter has now tracked across four vendors in three issues. Huawei's OceanStor M900 Context Memory Storage, introduced the same week at Huawei Connect, pools 64 petabytes and 40 terabytes per second of bandwidth specifically to hold shared KV caches for inference clusters. Silicon Motion's MonTitan, covered in Issue 06's Second Cut, pitched an enterprise SSD controller as a persistent memory tier for exactly this workload. Kioxia's CXL-attached NAND, from Issue 05, chases the same problem from the controller side with DRAM-class latency as the goal. Nvidia's own ICMSP standard, this newsletter's Issue 02 Uplevel term, formalized pushing overflow KV cache out to NVMe over RDMA in the first place, which is the plumbing every one of these products now builds on top of.

What's different about HPE's entry is who's making the claim and what stage it's at. This is a storage-systems vendor, not a controller or component maker, and the product is generally available today, not a concept or reference design. The physics behind the aggressive-sounding numbers checks out on paper: a long AI agent session can generate a KV cache north of 320GB, a figure Silicon Motion cited in Issue 06, well past what fits in a single GPU's onboard HBM, so anything that moves those bytes back to the GPU faster over RDMA instead of a generic storage stack should show a real speedup. The open question is how much of that 20x survives contact with production traffic instead of a vendor's own benchmark run.

Step back and the more interesting story is that every major storage vendor is racing to reposition its box as the answer to a memory problem that HBM shortages made worse and that DeepSeek's efficiency claims, covered in Issue 07's Deep Cut, argued might shrink on its own. Four vendors piling into the same pitch inside three issues is the market betting that DeepSeek's cache-shrinking architecture doesn't get replicated fast enough, or broadly enough, across the industry to make the problem go away before the next fiscal year.