Weekly signal for the people building and buying AI infrastructure: what moved, why it matters, what's next.
Samsung showed up with three different memory products this cycle, a NAND chip, an HBM concept, and an edge-storage concept, and all three lean on the same underlying trick. That is this issue's real story. Elsewhere it was a quieter stretch than last issue's benchmark fireworks: Solidigm inched toward a Nasdaq listing, Supermicro closed out a month-long storage summit, and Silicon Motion made the case that a fast enough SSD beats buying more HBM for the KV cache problem. Two dives, one term, and an honest note about how thin the wire was this week.
A persistent line on where the shortage stands, present every issue whether or not the picture actually moved.
Direction: Worsening.
This period: No new signal this issue, unchanged from Issue 05.
Driver: AI hyperscaler demand for DRAM, NAND, and HBM is outrunning capacity even as Samsung and SK hynix both report record bit shipments; HBM production is reallocating fab capacity away from conventional DRAM and NAND, tightening both further.
Watch for: Q3/Q4 2026 capacity guidance from Samsung, SK hynix, and Micron, and whether new fab investment (Kioxia/SanDisk's $31B Japan expansion) starts easing NAND allocation in 2027.
A running index of a few figures we track issue over issue, so the trend is visible, not just the snapshot. No fresh, comparable figure cleared our verification bar on any of the four core metrics this week, so the table below carries forward unchanged from Issue 05 rather than forcing a row that isn't there.
| Issue | Date | Metric | Value |
|---|---|---|---|
| Issue 03 | Aug 30, 2026 | 30TB enterprise SSD list price | $22,600 |
| Issue 04 | Sep 4, 2026 | 30TB enterprise SSD list price | $22,600 (flat) |
| Issue 05 | Sep 1, 2026 | DDR4 1Gx8 3200MT/s spot price | $44.54 (+2.08% WoW) |
| Issue 05 | Aug 31, 2026 | 512Gb TLC NAND wafer spot price | $20.71 (-0.90% WoW) |
Five things that happened, and why I'd pay attention to each one. It was a lighter week than usual on breaking news, which is itself worth saying plainly rather than papering over.
Samsung's zHBM concept stacks HBM directly on top of an accelerator die instead of beside it on an interposer, targeting roughly 8x the performance of HBM5, more than 10x the density, and 3x the energy efficiency. V10 BV-NAND, its first NAND built with wafer bonding, packs over 400 layers and 58% more density than the prior generation. A third concept, zNAND-O, applies the same bonding approach to four- and eight-die edge storage stacks. None of it has a shipping date past "after 2029" for the ambitious pieces.
SK hynix committed in an August 6 filing to update investors on Solidigm's strategic review by September 4 at the latest. A US asset manager pre-registered a Solidigm-focused ETF with the SEC less than a day before that deadline, the clearest signal yet that a listing has moved from speculation to execution. Reported terms point to a pre-IPO valuation near $35.3 billion, roughly four years after SK hynix paid about $9 billion for the NAND business.
The seventh annual Open Storage Summit, a month-long virtual series presented with theCUBE, closed September 3 after 12 sessions built around 38 speakers from 21 companies: AMD, DDN, Hammerspace, IBM, Intel, Kioxia, MinIO, Nutanix, Scality, Solidigm, VAST Data, Western Digital, Crusoe, and Iron Mountain among them. The stated focus was cost-efficient infrastructure for enterprise AI inference and agentic workloads.
The commercial agreement Google and Marvell signed July 29, disclosed August 19, covers more than AI inference accelerators: storage controllers, network interface controllers, memory interface controllers, and near-memory compute all sit inside the same warrant, which lets Google buy up to 58.97 million Marvell shares at $206.58 each as purchases hit milestones. Analysts read it less as a threat to Broadcom's TPU business and more as evidence Google is running a genuine multi-source custom-silicon program.
Worldwide external enterprise storage systems spending hit $9.9 billion in Q1 2026, up 22.9% year over year, a sharp acceleration from 3.9% growth for all of 2025 and 5.5% in Q4 2025. IDC attributes it to deferred refresh spending, component price inflation, and AI-driven demand landing at the same time.
A running snapshot, updated whenever a vendor discloses something new, not re-explained from scratch every week.
zHBM concept now quantified: roughly 8x HBM5 performance, more than 10x the memory density, 3x the energy efficiency, and under half the thermal resistance, by stacking HBM directly on the accelerator die instead of beside it on an interposer. Still no committed date past "after 2029."
Roadmap detailedHybrid bonding pushed from HBM4E to HBM5 after hitting a 775-micron packaging ceiling. Racing for 16-Hi HBM4 delivery to Nvidia by Q4 2026.
DelayedReportedly adding up to 60K HBM wafers per month toward roughly 100K by year end, with 12-Hi HBM4 for Vera Rubin heading toward half of output. Still racing for 16-Hi HBM4 by Q4 2026.
Capacity rampNew section this issue. A card per tracked storage systems vendor, ranked from the latest named analyst report, touched only when a fresh report actually drops. These entries currently reflect IDC's Q1 2026 tracker and the 2026 Gartner Magic Quadrant.
Broadest portfolio in the market; leaning on an AI-storage attach strategy across PowerScale and PowerStore to ride server deals into storage revenue.
Last updated Issue 01Slipped from 2nd to behind Huawei and HPE in the 2026 Magic Quadrant. AFX disaggregated architecture and the new AI Data Engine (AIDE); DGX SuperPOD-certified.
Last updated Issue 03Formerly Pure Storage, renamed February 2026. Number one on both Magic Quadrant axes for the second straight year; climbed to third on subscription-model adoption and AI-optimized platform revenue.
Last updated Issue 03Strong outside North America; among the fastest-growing suppliers by IDC count over the past two trackers.
Last updated Issue 01Folding storage into its broader AI factory and GreenLake positioning.
Last updated Issue 01IBM Storage Scale holds roughly 17% of the parallel file system market specifically; Storage Scale System 6000 is NVIDIA-certified for metadata-heavy training jobs.
Last updated Issue 01The Storage and Memory Signal reaches people who actually buy and operate AI storage and memory infrastructure, AI DevOps engineers, infra leads, and the executives they report to. If that's your buyer, this slot is available.
V10 BV-NAND, zHBM, and zNAND-O look like three separate announcements. They are one bet, wearing three costumes.
Samsung previewed zHBM at FMS 2026 in early August, then followed with a fuller technical rundown from its own Semiconductor Newsroom on September 5 covering three architectures at once: V10 BV-NAND, a shipping-adjacent NAND product; zHBM, a longer-horizon HBM concept; and zNAND-O, an edge-storage concept aimed at a different market entirely. Read separately, they're three roadmap slides. Read together, they're a single company deciding that wafer bonding, not incremental die shrinks, is the lever that gets it through the next decade of the memory wall.
Start with what's actually real. V10 BV-NAND is Samsung's first NAND built with wafer bonding rather than the conventional single-stack process, which is why the company calls it "BV," for Bonding V-NAND. Instead of building memory cells and control logic in one continuous stack, Samsung manufactures them on two separate wafers and bonds them together afterward. That decoupling is what let the company push past 400 layers while still gaining 58% density and cutting power by more than a quarter. This is the product with a real customer conversation happening now, not a slide for 2029.
zHBM is the ambitious one, and it's worth being honest about what "concept" means here: Samsung showed numbers, not silicon. The premise is that HBM's current arrangement, sitting beside a GPU or accelerator die on a 2.5D interposer, has a hard ceiling on how close memory can physically get to compute. zHBM removes the interposer and stacks DRAM directly on top of the processor. If the 8x performance and 10x density figures survive contact with an actual production line, that's a genuinely different architecture, not a faster HBM5. If they don't, this is where a lot of roadmap slides go to quietly disappear. Samsung has not given the market anything harder than "after 2029" to hold it to.
zNAND-O is the one nobody's talking about, and that's a mistake, because it points at a different problem entirely. Edge AI devices don't have the luxury of a data center's power budget or its parallel file system. zNAND-O applies the same bonding logic to compact 4- and 8-die stacks meant for low-latency, real-time inference at the edge, phones, cameras, industrial sensors, wherever the AI workload has to run without a fat pipe back to a cloud region. It's the quietest of the three announcements and arguably the one with the clearest path to shipping, since the engineering ambitions are far more modest than zHBM's.
What ties all three together isn't marketing, it's manufacturing economics. Wafer bonding, and the related hybrid-bonding technique covered in this newsletter's Issue 04 Uplevel Highlight, lets a chipmaker separate the problem of "make the memory cells" from the problem of "make the logic that talks to them." Once you can do that reliably at volume, you can apply it to a NAND chip, an HBM stack, or an edge storage module without reinventing the underlying bond for each one. Samsung is betting that the company that masters this once, across product lines, wins more than the company that ships one clever HBM generation and starts from scratch on the next.
MonTitan positions enterprise NVMe as a persistent memory tier for AI agents. The money behind it says the market believes the pitch.
Silicon Motion unveiled its next-generation MonTitan SSD Reference Design Kit on August 10, built around an updated PerformaShape architecture and PCIe 6.0 controller support, and the framing is specific: enterprise SSDs as a persistent memory layer for key-value cache offload, aimed squarely at AI agents that reason across many steps and hold long conversational context. Three days later, on August 13, the company closed $1.15 billion in zero-coupon convertible notes due 2031, upsized with a full greenshoe exercise. The stock kept climbing into this week on continued optimism about NAND controller demand.
The logic is straightforward once you see it. A long-context AI agent session generates a key-value cache that can outgrow the GPU's onboard HBM by a wide margin. When that happens, the system either evicts the cache and recomputes it later, burning latency, or moves it somewhere else and fetches it back when needed. This newsletter's Issue 02 Uplevel Highlight covered Nvidia's answer to that problem, ICMSP, a standard for pushing KV cache to NVMe over RDMA. Silicon Motion's pitch runs the same play from the controller side: build the SSD itself to behave like a memory-tier citizen rather than a traditional storage target, and sell that as the reason to buy its silicon over a generic NAND controller.
It's also a different bet than the one Kioxia made in this newsletter's Issue 05 Signal section. Kioxia wants to pair fast NAND with a CXL controller and use it as a partial DRAM substitute, cutting latency to a fraction of conventional NAND. Silicon Motion isn't chasing DRAM-class latency at all. It's arguing that for a cache tier that mostly needs capacity and won't be read on every token, ordinary enterprise NVMe, tuned specifically for this access pattern, is close enough to good and dramatically cheaper than provisioning more HBM or DRAM to hold it. Whether that argument holds depends entirely on how latency-sensitive a given agent workload actually is, and Silicon Motion has an obvious incentive to say the answer is "not very."
The size of the convertible raise is the part worth sitting with. A zero-coupon note at a 65% conversion premium is a bet that the market will reward this positioning specifically, not just NAND controllers generally. Whether that's a controller company reading the agentic AI market correctly, or a controller company borrowing heavily against a narrative that hasn't been proven at scale yet, is not something this week's stock move actually answers.
One piece of storage or memory vocabulary, explained properly, every week.
In plain English: spot price is what memory costs on the open market today. Contract price is what a buyer with a standing relationship already locked in, usually for a quarter at a time.
Most DRAM and NAND doesn't change hands one chip at a time on a public exchange. The bulk of it moves through negotiated supply agreements between chipmakers and their largest customers, hyperscalers, PC OEMs, module makers, renegotiated on a quarterly cadence and generally kept private. Contract price is sticky by design. It reflects a relationship, a volume commitment, and often a forecast both sides agreed to months earlier.
Spot price is the leftover market: smaller buyers, brokers, and distributors trading whatever supply isn't already locked into a contract, on public tracking services like TrendForce that publish daily or weekly quotes. Because it's thinner and less relationship-bound, spot price reacts to sentiment almost immediately, a rumor about a fab outage or a hyperscaler pulling forward an order can move it in a single session, while contract price won't budge until the next quarterly reset.
The gap between the two tells you where the market actually is. When spot trades meaningfully above contract, as it has through most of this shortage, it means buyers who don't have a contract are willing to pay a premium to get supply at all, a sign of genuine scarcity rather than just sticky pricing. When spot falls below contract, it usually means near-term demand has softened even if the official contract number hasn't caught up yet. This newsletter's Index tracks spot price specifically because it's the earlier signal, contract price mostly just confirms what spot already told you, a quarter later.
That's also why this issue's Index section carries no new row. Contract prices for 3Q26 finalized in July on strong AI and server demand, but the spot market TrendForce has been reporting since has stayed comparatively quiet, with NAND flash spot trading described as sluggish and DRAM spot trading described as subdued. Quiet spot trading isn't the same as a resolved shortage. It's closer to a market waiting to see whether Q4 capacity guidance from Samsung, SK hynix, and Micron changes the picture, which is exactly what this issue's Shortage Watch is also waiting on.
AI Infra Summit 2026, Santa Clara. About as close as this space gets to a dedicated conference. Expect vendors to time announcements around it.
Micron fiscal Q4 2026 earnings. The first hard numbers on how much of the reported 60K-wafer HBM capacity ramp actually materialized, and whether conventional DRAM allocation shifted alongside it.
OCP Global Summit 2026, San Jose McEnery Convention Center. The Open Compute Project's flagship event, themed "Scaling Innovation for the AI Era," and the last one before the Summit relocates to San Francisco's Moscone Center starting in 2027.
SC26, Chicago. The HPC and storage world's biggest annual gathering, and the first real venue where MLPerf Storage v3.0's results get argued over in person.